Image Sensor

ABSTRACT

An image sensor has a plurality of pixels, each pixel having a photodiode ( 12 ), a voltage amplifier ( 16 ) having gain magnitude greater than 1 and a sampling capacitor ( 18 ) charged by the voltage amplifier. In this arrangement, each pixel provides gain through voltage amplification. This enables the sampling capacitor to be kept to a low size, so that the pixel circuitry occupies the smallest possible space, thereby enabling large aperture pixels to be formed. A source-follower buffer transistor ( 49 ) is provided at the input to the voltage amplifier. This overcomes the effect of charge sharing resulting from the parasitic capacitances of the output transistor of the voltage amplifier.

This invention relates to image sensors, in particular having arrays of image sensing pixels, for example for use as solid state X-ray imaging devices.

There is significant interest in developing solid state X-ray imaging devices, to replace the image intensifiers currently used in hospitals.

Various pixel configurations have been proposed in which each pixel comprises a light sensitive element, such as a photodiode, and at least one switching device. For example, one known pixel design comprises a single thin film transistor (TFT) and a photodiode. During an exposure period, the TFT is turned off so that the photodiode is isolated. Incident light causes a minority carrier current to be produced, which causes the parasitic self-capacitance of the diode to be discharged. During the next readout, the capacitance of the diode is reset and the change in charge is detected by the amplifier.

It has also been proposed to provide in-pixel gain in order to improve the signal to noise ratio of the Image sensor pixel. This is particularly desirable in Flat Dynamic X-Ray Detection (FDXD). The in-pixel amplification is performed before additional electronic noise is introduced.

One way to achieve in-pixel gain is to include an additional storage/sampling capacitor within the pixel configuration, with the charge stored on the sampling capacitor being greater than the charge generated by the photodiode. The sampling capacitor charge can then be measured by the readout amplifier.

WO 01/57554 discloses a pixel configuration in which the voltage across the pixel photodiode (which is representative of the illumination level) is provided to a source follower circuit arrangement which acts as a unitary gain voltage buffer. The output voltage charges a sampling capacitor, and the gain of the pixel is dependent on the ratio of the capacitance of the sampling capacitor to the pixel capacitance. The circuit operates according to the principle of so-called “Double Correlated Sampling” (DCS). The double sampling approach eliminates noise induced by the resetting of the sampling capacitor and is particularly desirable for low noise amplification. DCS involves sampling the voltage across a sampling capacitor corresponding to a reset condition of the sensor element, so that the subsequent flow of charge to the sampling capacitor is representative of the change in voltage across the sensor element and not dependent on the reset state of the sensor element.

Whilst this circuit operates well, one problem with this approach is the area required for the sampling capacitor, which can limit the possible resolution which can be achieved. There is, however, a need to provide pixel gain with low noise.

It has been proposed by the applicant to provide voltage amplification within the pixel circuits. This enables a smaller sampling capacitor to be used.

However, a problem associated with the use of a voltage amplifier circuits arises as a result of the Miller effect. In particular, the input impedance of the voltage amplifier causes some of the input charge to be shared between an input storage capacitance and the parasitic gate-source capacitance of the drive transistor. The Miller effect tends to increase the apparent parasitic capacitance at this stage.

According to the invention, there is provided an image sensor comprising a plurality of pixels, each pixel comprising:

a light sensor element, a sensor voltage across the element varying depending on the light incident on the element;

a voltage amplifier having gain magnitude greater than 1; and

a sampling capacitor charged by the voltage amplifier,

wherein the voltage amplifier comprises first and second transistors in series, the input to the voltage amplifier being provided to the gate of the first transistor, and the output being defined by the junction between the first and second transistors,

and wherein each pixel further comprises a third transistor, the gate of the third transistor being connected to one terminal of the light sensor element, and the source of the third transistor being connected to the gate of the first transistor.

In this arrangement, each pixel provides gain through voltage amplification. This enables the sampling capacitor to be kept to a low size, so that the pixel circuitry occupies the smallest possible space, thereby enabling large aperture pixels to be formed. The amplifier arrangement of two series-connected transistors uses the requirement for equal source-drain currents to provide voltage amplification of the gate-source voltage signals. The third transistor acts as a buffer before signal amplification, and this overcomes the effect of charge sharing resulting from the parasitic capacitances of the first transistor of the voltage amplifier.

Although the self-capacitance of the light sensor element may be sufficient to store the photodiode voltage temporarily, each pixel preferably further comprises a pixel storage capacitor connected to the light sensor element. The capacitance of the sampling capacitor is then less than 10 times the capacitance of the pixel storage capacitor, preferably less than 2 times the capacitance of the pixel storage capacitor, and may be equal to the capacitance of the pixel storage capacitor.

Thus, the size of the sampling capacitor can be kept to a minimum.

The capacitance of the sampling capacitor may be in the range 0.5 pF to 3 pF, and the self-capacitance of light sensor or the capacitance of the pixel storage capacitor may also be in the range 0.5 pF to 3 pF. The gain magnitude of the voltage amplifier may be in the range 2 to 5.

The output of the voltage amplifier is preferably connected to one terminal of the sampling capacitor, the other terminal of the sampling capacitor being connected to the pixel output through an output switch. This output switch can be used both for connecting a charge sensitive amplifier to the output and for a resetting operation. Each pixel preferably further comprises an input switch for applying a fixed potential across the light sensor element, thereby providing a reset function.

The invention also provides a method of measuring light intensity of an image to be detected using a plurality of light sensor elements each forming a pixel of an image sensor, a sensor voltage across the elements varying depending on the light incident on the elements, the method comprising:

providing the sensor voltage to an in-pixel voltage amplifier through a source-follower buffer transistor;

amplifying the voltage provided by the source-follower buffer transistor using the in-pixel voltage amplifier having a gain magnitude greater than 1;

charging a sampling capacitor with the amplified voltage and measuring the flow of charge required to charge the sampling capacitor.

Preferably, a reset operation is carried out before amplifying the sensor voltage, the reset operation comprising applying a known potential to one terminal of the sampling capacitor and applying a known potential across the sensor element, the amplified voltage being subsequently applied to the other terminal of the sampling capacitor.

This reset operation samples the output of the voltage amplifier corresponding to a reset pixel, double correlated sampling can be implemented.

Examples of the present invention will now be described by way of example, with reference to and as shown in the accompanying drawings in which:

FIG. 1 shows schematically a pixel configuration for use in an image sensor proposed by the applicant;

FIG. 2 shows in more detail an implementation of the pixel circuit of FIG. 1;

FIG. 3 shows a first pixel circuit of the invention;

FIG. 4 shows timing diagrams to explain the operation of the circuit of FIG. 3;

FIG. 5 shows a second pixel circuit of the invention;

FIG. 6 shows a third pixel circuit of the invention; and

FIG. 7 shows an image sensor of the invention.

FIG. 1 shows in schematic form a pixel configuration proposed by the applicant, for use in a solid-state image sensor.

The pixel 10 comprises a light sensor element 12, in the form of a photodiode.

The photodiode signal is in the form of a current which is dependent on the light input and which flows for a defined time—the sample time. The signal to be sensed is thus a flow charge, which is a minority carrier current which discharges the self-capacitance of the photodiode during illumination. This flow of charge is converted to a voltage by a pixel capacitor 14.

A voltage across the photodiode thus varies depending upon the light incident on the photodiode. In the examples below, the pixel capacitor 14 is a separate component to the photodiode, but the photodiode self-capacitance can perform the same function.

In FIG. 1, the pixel capacitor 14 is connected between the photodiode output (the cathode) and ground. Instead, the pixel capacitor may be in parallel with the photodiode. The photodiode of each pixel is connected at its anode to a voltage supply line 15.

The voltage Vin provided by the photodiode is amplified by an in-pixel amplifier 16 with gain G, so that a sampling capacitor 18 at the output of the amplifier is charged to a greater voltage than the photodiode voltage. As a result, a greater flow of charge is required, and this charge flow is measured as the output of the pixel.

If the sampling capacitor 18 has the same capacitance as the pixel capacitor 14, the gain of the pixel is G, and there is no charge gain. However, the sampling capacitor 18 may be larger than the pixel capacitor 14 so that the circuit can implement voltage amplification as well as charge gain.

This circuit enables the size of the sampling capacitor to be reduced, so that the pixel circuit components can occupy a smaller space, thereby improving the optical aperture of the pixel.

A reset input switch 20 is provided at the input to the pixel, and this enables a rest voltage Vreset to be applied to the photodiode and pixel capacitor to reset the photodiode between read out cycles. An output switch 22 enables the output to be connected to a charge sensitive amplifier and also enables a reset sampling operation to be performed as described further below.

Before an exposure period, a reset operation is carried out by closing the reset input switch 20. This causes the photodiode to be charged to a known voltage. The voltage appearing at the output of the amplifier 16 is then sampled by closing the output switch 22 to charge the output plate of the sampling capacitor to a fixed potential, typically 0V. The output voltage corresponding to the amplified signal for a pixel in the reset condition is thus held across the sampling capacitor. The output switch 22 is then opened, as well as the input switch 20, and the pixel is illuminated.

The pixel capacitor 14 holds the resulting photodiode/pixel capacitor voltage, and this is amplified by the amplifier 16. As there is no charge path to the output plate of the sampling capacitor 22, the voltage on this plate rises with the output voltage of the amplifier. After illumination is complete, the output switch 22 is closed and the charge flow is measured to return the output plate of the sampling capacitor to 0V (i.e. to the same voltage applied to the sampling capacitor during the initial reset operation). Thus, the charge measured is independent of the voltage resulting from the reset operation, and in this way double correlated sampling is implemented.

FIG. 2 shows in more detail a first NMOS implementation of the pixel circuit of FIG. 1, and which may be implemented using amorphous silicon transistors. The same reference numerals are used as in FIG. 1 for the same components.

The input switch 20 is implemented as an input TFT (thin film transistor) 30 with its gate connected to a reset input control line 32. The output switch 22 is implemented as an output TFT 34 with its gate connected to an output control line 36. The amplifier 16 is implemented as first and second NMOS transistors 38, 40 which are connected in series between the voltage supply line 15 and ground.

When the amplifier is operating, the sampling capacitor is isolated by the output switch 22, so that the current flowing through the two transistors is constrained to be the same. The current through the transistor 40 is a function of the input voltage, which is the gate-source voltage. Similarly, the current through the transistor 38 is a function of the output voltage Vout, as the voltage between the output Vout and a fixed voltage bias 44 defines the gate-source voltage of the transistor 38. Thus, the amplifier stabilises when the output voltage is such as to match the source-drain current of the two transistors.

By appropriate design of the two transistors 38, 40, the amplifier provides voltage gain, by requiring a greater change in gate-source voltage for the transistor 38 than the change in gate-source voltage required for the transistor 40 in order to achieve the same change in source-drain current. The drain of each transistor 38 is connected to the fixed voltage supply line 15.

The transistor 38 can have its gate 44 connected to the power line 15, so that the gate and drain are connected together. This diode connection of the transistor 38 provides a diode-loaded amplifier arrangement.

The amplifier is inverting, and the gain provided may be in the range 1.5 to 10, preferably 2 to 5. The gain of the amplifier section is basically the square root of the ratio of the transconductances (g_(m)) of the two TFTs. The transconductance is proportional to the width to length ratio of the TFT channel, and can therefore be controlled by selection of the size and shape of the transistor channels. For example, for an amplifier with the upper TFT width 5 μm and lower TFT width 100 μm (both with length 5 μm), the ratio of widths is 20. This is directly (in first approximation) related to the transconductance g_(m), and so the gain is about 4.5. In reality, the TFTs are not actually working in the ideal saturation region, and so gain is slightly different.

For operation in (or close to) the saturation region, the TFTs have to be appropriately biased. The higher the gate voltage, the greater the DC bias current through the amplifier. This speeds up the action of the pixel. However, it also tends to reduce the working range of the amplifier and so reduces dynamic range.

The specific implementation of the amplifier as well the bias conditions for appropriate operation will be routine to those skilled in the art.

The light sensor element is connected to the gate of one of the transistors 40, and a bias voltage 44 is connected to the gate of the other transistor 38, the output of the voltage amplifier being defined at the connection between the first and second transistors.

A problem with this circuit is that some of the input charge is shared between the input storage capacitance 14 and the parasitic gate-source capacitance of the amplifier transistor 40. Miller effects tend to increase the apparent parasitic capacitance at this stage, particularly as the amplifier is inverting.

FIG. 3 shows a pixel circuit of the invention. The invention provides buffering of the signal voltage into the amplifier TFT 40. An additional source-follower transistor buffers the input into the amplifier transistor.

The pixel circuit of FIG. 3 uses the same reference numerals as the circuit of FIG. 2. The additional source-follower transistor is shown as 49. This acts as a source follower into the gate of the amplifier transistor 40. The gate of the amplifier transistor 40 thus tends to one threshold voltage below the gate voltage of the source-follower transistor 49.

The source follower transistor 49 has its source connected to the gate of the amplifier transistor 40, and the input voltage is provided to the gate of the source follower transistor 49. The drain of the source follower transistor is connected to the power supply line 15. This defines a non-inverting unitary gain buffer stage.

The additional source follower transistor 49 drives only the gate capacitance of the amplifier TFT 40 and is not disturbed in readout, so it can be made with small dimensions. This greatly reduces the size of the parasitic capacitance effective on the input storage capacitance 14. As the additional source follower transistor 49 is non-inverting and has no gain, the Miller effect is negligible. The larger Miller capacitance of the amplifier TFT 40 no longer effects the operation of the circuit as the buffer voltage-drives the amplifier input, so that the buffer replaces the lost charges.

FIG. 4 shows timing diagrams to explain the operation of the circuit of FIG. 3.

Plot 50 shows the exposure period during which the voltage on the pixel capacitor varies in dependence on the input voltage. During the exposure period, the input and output switches are open.

Plot 52 shows the operation of the output switch 22 and represents the signal applied to the output control line 36. Plot 54 shows the operation of the reset input switch 20 and represents the signal applied to the reset input control line 32. Plot 56 shows the operation of the charge measurement circuit connected to the output.

All pixels are illuminated simultaneously, and are subsequently read out in rows. Thus, each of the plots 52, 54, 56 may be applied in turn to the different rows of the array of pixels.

When signals stored in a row of pixels are to be read, the output switch for each column of pixels is first closed, and the respective charge sensitive amplifier then charges or discharges the sampling capacitor 18 until the voltage on the output plate is equal to the voltage of the charge sensitive amplifier. This is shown as plot 56. The charge sensitive amplifier has a virtual earth input, so that it holds the capacitor output plate to 0V, whilst the amplifier maintains the amplified output voltage because the voltage input to the amplifier is held by the pixel capacitor 14. The flow of charge is measured, and represents the change in voltage across the photodiode.

Each column may be associated with a charge sensitive amplifier, so that all columns of pixels are read simultaneously, row by row. However, multiplexing arrangements may be used to reduce the number of charge sensitive amplifiers required.

At the end of the charge measurement operation, the photodiode is reset, by the pulse of plot 54. This places a fixed voltage across the photodiode. As the output switch 22 remains closed, a charge can be stored across the sampling capacitor, so that the reset noise is effectively sampled, and in this way double correlated sampling is implemented.

The reset pulse then ends, and shortly afterwards the output switch opens in preparation for the next illumination period.

A reset switch may be connected in parallel with the sampling capacitor 18 operated synchronously with the input switch 20, for assisting the discharge of the sampling capacitor after the charge measurement cycle. In this case, the output switch is preferably opened at this time, as shown in dotted lines in plot 52.

FIG. 5 shows a second implementation of the pixel circuit of FIG. 3, which is a CMOS (polycrystalline silicon) implementation. The only difference between FIG. 5 and FIG. 3 is that the transistor 38 is implemented as a PMOS transistor, with the source and gate connected together.

FIG. 6 shows a modification to the pixel circuit of FIG. 3, in which a current source 58 provides biasing of the source follower transistor 49. This can be used if the pixel circuit is to be operated at high speed.

FIG. 7 shows a known X-ray examination apparatus which includes an X-ray source 60 for irradiating an object 62 to be examined, for example a patient to be radiologically examined, by means of an X-ray beam 64. Due to local differences in the X-ray absorption within the patent, an X-ray image is formed on an X-ray-sensitive surface 66 of the X-ray detector 68.

It is known to use as the X-ray detector 68 a solid state optical image sensor. The incident X-ray radiation is converted into light using a phosphor scintillator 66. This light can be detected by the solid-state device 68. Alternatively, an X-ray sensitive photoconductor can be used to convert the X-rays directly into electrons.

The pixel design of the invention is suitable for use in the solid state optical image sensor.

Various modifications will be apparent to those skilled in the art. 

1. An image sensor comprising a plurality of pixels, each pixel comprising: a light sensor element (12), a sensor voltage across the element varying depending on the light incident on the element (12); a voltage amplifier (16) having gain magnitude greater than 1; and a sampling capacitor (18) charged by the voltage amplifier, wherein the voltage amplifier comprises first (40) and second (38) transistors in series, the input to the voltage amplifier being provided to the gate of the first transistor (40), and the output being defined by the junction between the first and second transistors (40,38), and wherein each pixel further comprises a third transistor (49), the gate of the third transistor being connected to one terminal of the light sensor element (12), and the source of the third transistor (49) being connected to the gate of the first transistor (40).
 2. An image sensor as claimed in claim 1, wherein each pixel further comprises a pixel storage capacitor (14) connected to the light sensor element (12).
 3. An image sensor as claimed in claim 2, wherein the capacitance of the sampling capacitor (18) is less than 10 times the capacitance of the pixel storage capacitor (14).
 4. An image sensor as claimed in claim 3, wherein the capacitance of the sampling capacitor (18) is less than 2 times the capacitance of the pixel storage capacitor (14).
 5. An image sensor as claimed in claim 4, wherein the capacitance of the sampling capacitor (18) is approximately equal to the capacitance of the pixel storage capacitor (14).
 6. An image sensor as claimed in claim 3, 4 or 5, wherein the capacitance of the sampling capacitor (18) is in the range 0.5 pF to 3 pF, and the capacitance of the pixel storage capacitor (14) is in the range 0.5 pF to 3 pF.
 7. An image sensor as claimed in claim 1, wherein the capacitance of the sampling capacitor (18) is less than 10 times a self-capacitance of the light sensor element (12).
 8. An image sensor as claimed in claim 7, wherein the capacitance of the sampling capacitor (18) is less than 2 times the self-capacitance of the light sensor element (12).
 9. An image sensor as claimed in claim 7 or 8, wherein the capacitance of the sampling capacitor (18) is in the range 0.5 pF to 3 pF, and the self-capacitance of light sensor (12) is in the range 0.5 pF to 3 pF.
 10. An image sensor as claimed in any preceding claim, wherein the gain magnitude of the voltage amplifier (16) is in the range 2 to
 5. 11. An image sensor as claimed in any preceding claim, wherein a bias voltage (44) is connected to the gate of the second transistor (38).
 12. An image sensor as claimed in claim 11, wherein the output of the voltage amplifier (16) is connected to one terminal of the sampling capacitor (18), the other terminal of the sampling capacitor (18) being connected to the pixel output through an output switch (22;34).
 13. An image sensor as claimed in any preceding claim wherein each pixel further comprises an input switch (20;30) for applying a fixed potential (Vreset) across the light sensor element.
 14. A method of measuring light intensity of an image to be detected using a plurality of light sensor elements (12) each forming a pixel of an image sensor, a sensor voltage (Vin) across the elements varying depending on the light incident on the elements, the method comprising: providing the sensor voltage (Vin) to an in-pixel voltage amplifier through a source-follower buffer transistor; amplifying the voltage provided by the source-follower buffer transistor using the in-pixel voltage amplifier (16) having a gain magnitude greater than 1; charging a sampling capacitor (18) with the amplified voltage (Vout) and measuring the flow of charge required to charge the sampling capacitor (18).
 15. A method as claimed in claim 14, wherein a reset operation is carried out before amplifying the voltage provided by the source-follower buffer transistor, the reset operation comprising applying a known potential to one terminal of the sampling capacitor (18) and applying a known potential (Vreset) across the sensor element, the amplified voltage (Vout) being subsequently applied to the other terminal of the sampling capacitor (18).
 16. A method as claimed in claim 14 or 15, wherein the capacitance of the sampling capacitor (18) is less than 10 times the capacitance of a pixel storage capacitor (14) of the pixel.
 17. A method as claimed in claim 16, wherein the capacitance of the sampling capacitor (18) is less than 2 times the capacitance of the pixel storage capacitor (14).
 18. A method as claimed in claim 17, wherein the capacitance of the sampling capacitor (18) is approximately equal to the capacitance of the pixel storage capacitor (14).
 19. A method as claimed in any one of claims 14 to 18, wherein the gain magnitude of the voltage amplifier (16) is in the range 2 to
 5. 